同步FIFO案例 --- 引數化的module

一、同步FIFO設計要點

二、同步FIFO範例

module cm_slv_dec_sync_fifo #(
  parameter    FIO_DATA_WIDTH = 32'd32,
  parameter    FIO_DATA_WIDTH = 32'd32
) (
  input                                fifo_rstb,
  input                                fifo_clk,
  //write clock domain
  input                                fifo_wr_req,
  input  [FIFO_DATA_WIDTH-1:0]         fifo_wr_data,
  output                               fifo_wr_ack,
  //read clock domain
  output                               fifo_rd_req,
  output  [FIFO_DATA_WIDTH-1:0]        fifo_rd_data,
  input                                fifo_rd_ack,
)

localparam FIFO_PTR_BIT = clog2(FIFO_DATA_DEPTH);

integer j;

reg [FIFO_DATA_WIDTH-1:0]              fifo_mem[FIFO_DATA_DEPTH-1:0];
reg [FIFO_PTR_BIT:0]                   wr_ptr;
reg [FIFO_PTR_BIT:0]                   rd_ptr;

write